View TC7MET573AFK_332788.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TC7MET573AFK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC7MET573AFK
Octal D-Type Latch with 3-State Output
The TC7MET573AFK is an advanced high speed CMOS octal latch with 3-state output fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and a output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. Weight: 0.016 g (typ.) The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (*) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. *: output in off state
Features
* * * * * * * High speed: tpd = 7.7 ns (typ.) (VCC = 5 V) Low power dissipation: ICC = 4 A (max) (Ta = 25C) Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min) Power down protection is provided on all inputs and outputs. Balanced propagation delays: tpLH tpHL - Low noise: VOLP = 1.5 V (max) Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc.) 573 type.
000630EBA1
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
2000-07-04
1/6
TC7MET573AFK
Pin Assignment (top view) IEC Logic Symbol
OE
OE
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11
VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE
LE
(1) (11)
EN C1
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
(2) (3) (4) (5) (6) (7) (8) (9)
1D
(19) (18) (17) (16) (15) (14) (13) (12)
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
GND 10
Truth Table
Inputs
OE
Outputs D X X L H Z Qn L H
LE X L H H
H L L L
X: Don't care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
D0 2 D
D1 3 D
D2 4 D
D3 5 D
D4 6 D
D5 7 D
D6 8 D
D7 9 D
11 LE
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
1
OE
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
2000-07-04
2/6
TC7MET573AFK
Maximum Ratings
Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating -0.5~7.0 -0.5~7.0 -0.5~7.0 (Note1) Unit V V V mA (Note3) mA mA mA mW C
-0.5~VCC + 0.5 (Note2) -20 20 25 75 180 -65~150
Note1: Output is off-state Note2: High or low state. IOUT absolute maximum rating must be observed. Note3: VOUT < GND, VOUT > VCC
Recommended Operating Conditions
Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time Symbol VCC VIN VOUT Topr dt/dv Rating 4.5~5.5 0~5.5 0~5.5 0~VCC -40~85 0~20 (Note4) (Note5) C ns/V Unit V V V
Note4: Output in off state Note5: High or low state
2000-07-04
3/6
TC7MET573AFK
Electrical Characteristics DC Characteristics
Characteristics High level Low level High level Output voltage Low level VOL Symbol VIH VIL VOH Test Condition VCC (V) Input voltage VIN = VIH IOH = -50 A or VIL IOH = -8 mA VIN = VIH IOL = 50 A or VIL IOL = 8 mA VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5 V or GND VIN = VCC or GND Per input: VIN = 3.4 V Other input: VCC or GND VOUT = 5.5 V 0 4.5~5.5 4.5~5.5 4.5 4.5 4.5 4.5 5.5 0~5.5 5.5 5.5 Min 2.0 4.4 3.94 Ta = 25C Typ. 4.5 0 Max 0.8 0.1 0.36 0.25 0.1 4.0 1.35 0.5 Ta = -40~85C Min 2.0 4.4 3.80 Max 0.8 0.1 0.44 2.50 1.0 40.0 1.50 5.0 A A A mA A V V Unit
3-state output off-state current Input leakage current
IOZ IIN ICC
Quiescent supply current ICCT Output leakage current IOPD
Timing Requirements (Input: tr = tf = 3 ns)
Characteristics Minimum pulse width (LE) Minimum set-up time Minimum hold time Symbol tw (H) tw (L) ts th Test Condition VCC (V) 5.0 0.5 5.0 0.5 5.0 0.5 Ta = 25C Typ. Limit 6.5 1.5 3.5 Ta = -40~85C Limit 8.5 1.5 3.5 ns ns ns Unit
2000-07-04
4/6
TC7MET573AFK
AC Characteristics (Input: tr = tf = 3 ns)
Characteristics Propagation delay time (LE-Q) Propagation delay time (D-Q) 3-state output enable time Symbol tpLH tpHL tpLH tpHL tpZL tpZH tpLZ tpHZ tosLH tosHL CIN COUT CPD Test Condition VCC (V) CL (pF) 5.0 0.5 15 50 5.0 0.5 15 50 15 50 50 50 Min (Note7) Ta = 25C Typ. 7.7 8.5 5.1 5.9 6.3 7.1 8.8 4 9 25 Max 12.3 13.3 8.5 9.5 10.9 11.9 11.2 1.0 10 Ta = -40~85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 13.5 14.5 9.5 10.5 12.5 13.5 12.0 1.0 10 ns ns pF pF pF ns ns ns Unit
RL = 1 k RL = 1 k
5.0 0.5 5.0 0.5 (Note6) 5.0 0.5
3-state output disable time Output to output skew Input capacitance Output capacitance Power dissipation capacitance
Note6: Parameter guaranteed by design. tosLH = |tpLHm - tpLHn|, tosHL = |tpHLm - tpHLn| Note7: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD VCC fIN + ICC/8 (per latch) And the total CPD when n pcs. of latch operate can be gained by the following equation: CPD (total) = 14 + 11 n
Noise Characteristics (Input: tr = tf = 3 ns)
Characteristics Quiet output maximum dynamic Quiet output minimum dynamic VOL VOL VIH VIL Symbol VOLP VOLV VIHD VILD Test Condition VCC (V) CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF 5.0 5.0 5.0 5.0 Ta = 25C Typ. 1.1 -1.1 Limit 1.5 -1.5 2.0 0.8 V V V V Unit
Minimum high level dynamic input voltage Maximum low level dynamic input voltage
2000-07-04
5/6
TC7MET573AFK
Package Dimensions
Weight: 0.03 g (typ.)
2000-07-04
6/6

▲Up To Search▲

Price & Availability of TC7MET573AFK

	To Download TC7MET573AFK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .